王源博士
联系电话:010****7910
  • 所在单位:北京大学
  • 所在城市:北京
  • 邮箱:wan****@pku.edu.cn
  • 通讯地址:北京市海淀区燕园街道颐和园路5号
详细 · 介绍
Expert introduction

教育背景

2006年,北京大学,微电子学与固体电子学,理学博士

工作经历

2006/2008/2017,北京大学信息科学技术学院讲师/副教授/教授

2019,微电子器件与电路教育部重点实验室主任

2022,北京大学集成电路学院教授


研究成果

1. 近期论文

1) Qiao Xin, Song Jiahao, Tang Xiyuan*, Luo Haoyang, Pan Nanbing, Cui Xiaoxin, Wang Runsheng*, Wang Yuan*; A 65nm 73Kb SRAM-Based Computing-In-Memory Macro with Dynamic-Sparsity Controlling; IEEE Transactions on Circuits and Systems II: Brief Paper, June 2022, 69(6): 2977-2981.

2) Shen Zilong, Wang Yize, Li Yunhao, Zhang Xing*, Wang Yuan*; A Scalable Model for Snapback Characteristics of Circuit-Level ESD Simulation; IEEE Transactions on Circuits and Systems II: Brief Paper, March 2022, 69(3): 1547-1551.

3) Wang Yize, Wang Yuan*; Modeling Study of Power-on and Power-off System-level Electrostatic Discharge Protection; IEEE Transactions on Electromagnetic Compatibility, Aug 2021, 63(4): 979-987.

4) Song Jiahao, Wang Yuan*, Guo Minguang, Ji Xiang, Cheng Kaili, Hu Yixuan, Tang Xiyuan, Wang Runsheng*, Huang Ru; TD-SRAM: Time-Domain based In-Memory Computing Macro for Binary Neural Networks; IEEE Transactions on Circuits and Systems I: Regular Paper, Aug. 2021, 68(8): 3377-3387.

5) Kuang Yisong, Cui Xiaoxin*, Zhong Yi, Liu Kefei, Zou Chenglong, Wang Yuan*, Yu Dunshan, Huang Ru; A 64K-neuron 64M-synapse 2.64pJ/SOP Neuromorphic Chip with All Memory on Chip for Artificial General Intelligence in 65nm CMOS; IEEE Transactions on Circuits and Systems II: Brief Paper, July 2021, 68(7): 2655-2659.

6) Zhang Yawen, Wang Runsheng*, Zhang Xinyue, Wang Yuan*, Huang Ru; Parallel Hybrid Stochastic-Binary-Based Neural Network Accelerators; IEEE Transactions on Circuits and Systems II: Brief Paper, Dec. 2020, 67(12): 3387-3391.

7) Wang Yize, Wang Yuan*; A New Method to Correlate Human Body Model and Transmission Line Pulse Based on RC Thermal Equivalent Model; IEEE Transactions on Electron Devices, Sept. 2020, 67(9): 3775-3780.

8) Lu Guangyi, Wang Yuan*, Wang Yize, Zhang Xing*; Low-leakage ESD Power Clamp Design with Adjustable Triggering Voltage for Nano-scale Applications; IEEE Transactions on Electron Devices, Sept. 2017, 64(9): 3569-3575.

9) Lu Guangyi, Wang Yuan*, Wang Yize, Zhang Xing*; Insights into the Power-off and Power-on Transient Performance of Power-rail ESD Clamp Circuits; IEEE Transactions on Device and Materials Reliability, Sept. 2017, 17(3): 577-584.

10) Lu Guangyi, Wang Yuan*, Zhang Xing; Transient and Static Hybrid-triggered Active Clamp Design for Power-rail ESD Protection; IEEE Transactions on Electron Devices, Dec. 2016, 63(12): 4654-4660.


2. 著作

王源,贾嵩,崔小欣,王润声,甘学温,超大规模集成电路分析与设,2014,北京大学出版社


3. 科研项目

国家自然科学基金重点项目,基于Nor Flash的存算一体人工智能芯片和系统研究

国家重点研发计划项目,新型神经形态器件与电路研究